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Big news about UVVM

Since we merged with Bitvis, Inventas has been the primary developer of the UVVM platform and has continuously been developing new VVCs (VHDL Verification Components) and creating features such as scoreboard, VVC transaction information, monitors, error injection capability, property checkers, specification coverage tracking and so on.

Launching UVVM steering committee

Today we are pleased to announce that further management and development of the verification methodology will be handed over to an independent steering committee. The first two members in the committee will be Inventas and EmLogic, the two leading VHDL development and verification companies in Norway. In the following period the committee will be expanded to include additional members from the VHDL-community. We believe that a larger contributing community will make UVVM a better and more powerful tool in the years to come. Stay tuned for more updates on UVVM and the steering committee on uvvm.org.

Get the newest updates at FPGA verification day 2021

The 2021 FPGA Verification Day event at September 23rd and will also this year be held online, with a program that consist of several exciting topics; the future of the Lattice-Nexus platform, clock domain crossing and its importance in FPGA verification, cloud costs and productivity, functional verification with Modelsim, and UVVM and the advantages of this methodology for FPGA verification. At this event there will also be announced some new exciting features coming to UVVM soon.

Close collaboration with ESA

In 2017 ESA (European Space Agency) and NOSA (Norwegian Space Agency) awarded UVVM a contract to extend functionality and improve the quality of UVVM. These features was published as open source in 2019, and now ESA and NOSA are again backing UVVM in a new project to enhance the functionality, allowing for even better and more reusable testbenches.

With the support from ESA and NOSA, UVVM has become the number one verification methodology worldwide, and this has given the VHDL community an even more efficient verification framework for writing structured testbenches.

What is UVVM and why use it?

  • UVVM (Universal VHDL Verification Methodology) is the world's largest free open source VHDL verification methodology.
  • UVVM is designed to reduce development time, making structured and reusable testbenches, with an easy-to-understand API and with full verbosity control.
  • At Inventas we use UVVM in high-end space projects such as RIMFAX Mars 2020, and all other projects where possible.
  • UVVM is available to download for free from GitHub at https://github.com/UVVM/UVVM


Lars Guntveit
Avdelingsleder, Asker

Register for the The 2021 FPGA Verification Day event at September 23rd, to get the newest updates about UVVM.

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